HT32F61052
32-Bit Arm® Cortex®-M0+ 5V Power Delivery MCU with BMS
General Information
The Holtek device is a high performance, low power consumption 32-bit microcontroller based around an Arm® Cortex®-M0+ processor core. The Cortex®-M0+ is a next-generation processor core which is tightly coupled with Nested Vectored Interrupt Controller (NVIC), SysTick timer and including advanced debug support.
The device operates at a frequency of up to 60 MHz with a Flash accelerator to obtain maximum efficiency. It provides up to 128 KB of embedded Flash memory for code/data storage and up to 16 KB of embedded SRAM memory for system operation and application program usage. A variety of peripherals, such as Hardware Divider DIV, PDMA, ADC, I²C, UART, USART, SPI, MCTM, GPTM, PWM, BFTM, LEDC, EBI, CRC-16/32, 96-bit Unique ID, RTC, WDT, SW-DP (Serial Wire Debug Port), etc., are also implemented in the device. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications.
The device also includes an accumulative cell voltage monitor and a high accuracy voltage regulator, which is suitable for use in 6 cell Li-ion rechargeable battery applications. The accumulative cell voltage monitor is used to monitor an accumulative voltage from 1 to N and output the divide-by-N voltage to the analog multiplexer with a ±0.5 % divided ratio accuracy which can then be connected the integrated A/D converter channel for measurement.
The device also includes USB Power Delivery (PD) PHY communication protocols and are compliant with USB PD 3.2/PPS specification.
The above features ensure that the device is suitable for use in a wide range of PD applications, especially in areas such as power bank, car charger and various products powered by PD protocol.
Feature Details
| Attribute | Value |
|---|---|
| Core |
|
| On-chip Memory |
|
| Flash Memory Controller – FMC |
|
Reset Control Unit – RSTCU
| Attribute | Value |
|---|---|
| Supply supervisor |
|
Feature Details
| Attribute | Value |
|---|---|
| Clock Control Unit – CKCU |
|
Power Management – PWRCU
| Attribute | Value |
|---|---|
| VDD power supply | 2.5 V ~ 5.5 V |
| Integrated 1.5 V LDO regulator for MCU core, peripherals and memories power supply | Available |
| VDD and VCORE power domains | Available |
| Three power saving modes | Sleep, Deep-Sleep1, Deep-Sleep2 |
Feature Details
| Attribute | Value |
|---|---|
| PD PHY |
|
Accumulative Cell Voltage Monitor
| Attribute | Value |
|---|---|
| 5 V / 30 mA internal Voltage Regulator with ±1 % accuracy | Available |
| Accumulative Cell Voltage Monitor 6-to-1 Analog Multiplexer with divided ratio accuracy: | (1/n ± 0.5 %) |
Feature Details
| Attribute | Value |
|---|---|
| External Interrupt / Event Controller – EXTI |
|
| Analog to Digital Converter – ADC |
|
| I/O Ports – GPIO |
|
Motor Control Timer – MCTM
| Attribute | Value |
|---|---|
| 16-bit up, down, up/down auto-reload counter | Available |
| Up to 4 independent channels | Available |
| 16-bit programmable prescaler that allows division of the prescaler clock source by any factor | between 1 and 65536 to generate the counter clock frequency |
| Input Capture function | Available |
| Compare Match Output | Available |
| PWM waveform generation with Edge-aligned and Center-aligned Counting Modes | Available |
| Single Pulse Mode Output | Available |
| Complementary Outputs with programmable dead-time insertion | Available |
| Supports 3-phase motor control and hall sensor interface | Available |
| Break input signals to assert the timer output signals in reset state or in a known state | Available |
General-Purpose Timer – GPTM
| Attribute | Value |
|---|---|
| 16-bit up, down, up/down auto-reload counter | Available |
| Up to 4 independent channels | Available |
| 16-bit programmable prescaler that allows division of the prescaler clock source by any factor | between 1 and 65536 to generate the counter clock frequency |
| Input Capture function | Available |
| Compare Match Output | Available |
| PWM waveform generation with Edge-aligned and Center-aligned Counting Modes | Available |
| Single Pulse Mode Output | Available |
| Encoder interface controller with two inputs using quadrature decoder | Available |
Feature Details
| Attribute | Value |
|---|---|
| Pulse-Width-Modulation Timer – PWM |
|
| Basic Function Timer – BFTM |
|
| Watchdog Timer – WDT |
|
| 24-bit up-counter with a programmable prescaler | Available |
| Alarm function | Available |
| Interrupt and Wake-up event | Available |
| Inter-integrated Circuit – I²C |
|
Serial Peripheral Interface – SPI
| Attribute | Value |
|---|---|
| Supports both master and slave modes | Available |
| Frequency of up to (fPCLK/2) MHz for the master mode and (fPCLK/3) MHz for the slave mode | Available |
| FIFO Depth | 8 levels |
| Multi-master and multi-slave operation | Available |
Universal Synchronous Asynchronous Receiver Transmitter – USART
| Attribute | Value |
|---|---|
| Supports both asynchronous and clocked synchronous serial communication modes | Available |
| Programmable baud rate clock frequency up to (fPCLK/16) MHz for asynchronous mode and (fPCLK/8) MHz for synchronous mode | Available |
| Full duplex communication | Available |
| Supports LIN (Local Interconnect Network) mode | Available |
| Supports single-wire mode | Available |
| Fully programmable serial communication characteristics including: |
|
| Error detection | Parity, overrun and frame error |
| Auto hardware flow control mode – RTS, CTS | Available |
| IrDA SIR encoder and decoder | Available |
| RS485 mode with output enable control | Available |
| FIFO Depth | 8-level for both receiver and transmitter |
Universal Asynchronous Receiver Transmitter – UART
| Attribute | Value |
|---|---|
| Asynchronous serial communication operating baud-rate clock frequency up to (fPCLK/16) MHz | Available |
| Full duplex communication | Available |
| Supports LIN (Local Interconnect Network) mode | Available |
| Supports single-wire mode | Available |
| Fully programmable serial communication characteristics including: |
|
| Error detection | Parity, overrun and frame error |
Cyclic Redundancy Check – CRC
| Attribute | Value |
|---|---|
| Support CRC16 polynomial: 0x8005, | X16+X15+X2+1 |
| Support CCITT CRC16 polynomial: 0x1021, | X16+X12+X5+1 |
| Supports IEEE-802.3 CRC32 polynomial: 0x04C11DB7, | X32+X26+X23+X22+ X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1 |
| Supports 1’s complement, byte reverse & bit reverse operation on data and checksum | Available |
| Supports byte, half-word & word data size | Available |
| Programmable CRC initial seed value | Available |
| CRC computation executed in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit data | Available |
| Supports PDMA to complete a CRC computation of a block of memory | Available |
Peripheral Direct Memory Access – PDMA
| Attribute | Value |
|---|---|
| 6 channels with trigger source grouping | Available |
| 8-bit, 16-bit and 32-bit width data transfer | Available |
| Supports linear address, circular address and fixed address modes | Available |
| 4-level programmable channel priority | Available |
| Auto reload mode | Available |
| Supports trigger source: | ADC, SPI, UART, USART, I²C, MCTM, GPTM, PWM and software request |
Feature Details
| Attribute | Value |
|---|---|
| Hardware Divider – DIV |
|
LED Controller – LEDC
| Attribute | Value |
|---|---|
| Supports 8-segment digital displays up to a maximum of 10 | Available |
| Supports 8-segment digital displays with common anode or common cathode | Available |
| Support frame interrupt | Available |
| Three clock sources | LSI, LSE and PCLK |
| The LED light on/off times can be controlled using the dead time setting | Available |
External Bus Interface – EBI
| Attribute | Value |
|---|---|
| Programmable interface for various memory types | Available |
| Translate the AHB transactions into the appropriate external device protocol | Available |
| Individual chip select signal for per memory bank | Available |
| Programmable timing to support a wide range of devices | Available |
| Automatic translation when AHB transaction width and external memory interface width is different | Available |
| Write buffer to decrease the stalling of the AHB write burst transaction | Available |
| Multiplexed and non-multiplexed address and data line configurations |
|
Feature Details
| Attribute | Value |
|---|---|
| Unique Identifier – UID |
|
| Debug Support |
|
Package and Operation Temperature
| Attribute | Value |
|---|---|
| 64-pin LQFP package | Available |
| Operation temperature range | -40 °C to 105 °C |
Resources
| Title | Date | File Size | Language | Download |
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